The present disclosure relates to a semiconductor device on which a stack of semiconductor chips is mounted.
To achieve high density in a small size, a semiconductor chip package has a structure in which multiple semiconductor chips are stacked and mounted. Known examples of such a structure for stacking semiconductor chips include a chip-on-chip (COC) connection structure in which terminals provided to circuit surfaces of semiconductor chips are connected to each other.
Japanese Unexamined Patent Publication No. 2013-30568 discloses a COC structure in which a chip expansion portion is provided to surround a periphery of a lower semiconductor chip. In this structure, a wire is provided on the chip expansion portion and connected to a terminal of the lower semiconductor chip. This wire and an external electrode of a package substrate are connected together via a bonding wire.
Japanese Unexamined Patent Publication No. 2012-169440 discloses a COC structure in which a first semiconductor chip is embedded in a resin layer so that a terminal of the first semiconductor chip appears on a surface of the resin layer, and a second semiconductor chip is provided on the first semiconductor chip. In this structure, a wiring layer is provided on a surface of the resin layer and connected to an external terminal of a semiconductor device. Terminals such as a bump included in the second semiconductor chip are connected to this wiring layer.